In both planar and FinFET technologies, different gate lengths are commonly used on a single die to serve multiple electrical purposes. For example, it is common to integrate both a short channel device and a long channel device on a same die. The short channel device, e.g., is typically a high performance device such as a logic device, memory device, ring oscillators, etc. From device perspective, short gate height is also preferred for increased device performance, e.g., increased performance of a ring oscillator (RO) (e.g., around 1 nm to 1% RO).
In such integration schemes, the long channel devices typically have a higher density concentration on the die than the short channel devices. For example, the power mask which defines the high power gate with thick dielectric layer and input/output areas are usually built with large gate length, e.g., Lg in high density areas. And, polishing tungsten or other gate metals, e.g., chemical mechanical polishing (CMP), during gate fabrication processes, tends to remove more material at the high gate density area than the lower density gate area due to loading effects. This, in turn, raises the risk of fin exposure for gates in high density areas, e.g., long channel devices. Accordingly, due to the fin exposure issue, it becomes ever more difficult to lower the gate height of short channel devices, without degrading device performance of the long channel devices.